A 2-GHZ FREQUENCY MULTIPLIER BASED ON DIGITAL DELAY LOCK LOOP IN 65 NM CMOS
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Generally phase lock loops (PLLs) are utilized in the implementation of the conventional clock generators and frequency multipliers. However there are some issues happened during designing PLLs. First of all, PLLs has a stability issue due to its higherorder systems. And this issue will cause the change of the loop bandwidth when PVT is different. Secondly, in PLLs, the output of the VCO will be fed back to the loop, which causes a peak phase error unexpectedly larger than the desired phase variation since jitter is accumulating over the oscillation cycles. These issues will make the design of a PLLbased frequency multiplier more complicated and challenging. In order to solve these issues, this thesis presents a 2-GHz frequency multiplier based on digital delay lock loop. In this design when the DLL is locked the digital DLL operated in the open-loop mode will reduce the jitter and power consumption due to dithering in the lock condition. In this design a compensation structure is proposed to keep track of any potential phase error caused by environmental variations. The reference input frequency is 500M Hz. This frequency multiplier is designed and fabricated in a 65nm CMOS. The thesis also provides theory and simulation results on frequency multiplier for readers.